The present invention relates to a thin film transistor structure, a method of manufacturing the same and a display device including the same, more particularly to a thin film transistor capable of realizing a high definition display without causing a signal delay and providing a large display screen by making a gate wiring which is connected to the thin film transistor have a large cross sectional area while reducing floating capacitance, a method of manufacturing the same, and a display device including the same.
A liquid crystal display using a thin film transistor (hereinafter referred to as a TFT) has been widely used as a display device in apparatuses such as computers, cellular telephones, watches and television sets to perform various displays. Particularly, a large screen and a high definition of a display device using the TFT have been demanded in recent years accompanied with increases in capability and storage capacitance of the computers and the like. To achieve the large screen and the high definition of the display device using the TFT, it is necessary to prevent a signal propagation delay by reducing resistivity particularly of a gate wiring. Therefore, lowering of resistivity of material forming the gate wiring has been investigated, and materials having low resistivity such as Al and Cu are starting to be adopted in stead of materials having relatively high resistivity such as Mo, MoW and MoTa.
However, when studying a 30-inch display device, in which the material of very low resistivity such as the foregoing Cu is used and also a definition is measured on diagonal lines thereof under a condition that a switching speed of the TFT is ignored, it turns out to be difficult to achieve a high definition of 200 ppi or higher with resistivity of the present gate wiring. This is because the definition of the display device depends on both resistivity of the material and a cross sectional area thereof even if material of low resistivity is used.
Specifically, to achieve the large screen and the high definition in the display device using the TFT, the cross sectional area of the gate wiring must be made large in addition to using the material with low resistivity. However, when a horizontal planar area of a gate electrode is expanded to increase the cross sectional area of the gate wiring, an aperture ratio of a pixel electrode is necessarily reduced, and additionally, a capacitor is formed between the gate wiring and other wirings or the gate electrode, thus producing floating capacitor. Accordingly, a transmission delay of signals may occur. Furthermore, though a thickness of the gate wiring can be simply increased, the mere increase in the thickness of the gate wiring causes another disadvantage that other wirings such as a signal wiring crossing the gate wiring are broken down.
Moreover, in terms of a manufacturing method of the gate wiring, the gate wiring is formed conventionally by a vapor deposition method such as a sputtering method. Although it is possible to increase the thickness of the gate wiring significantly since a film growth rate is low in the conventional vapor deposition method such as the sputtering method, this method may cause disadvantages in manufacturing such as a low yield and a high cost. Accordingly, the gate wiring must be manufactured by a more efficient method.
In order to scale down wirings formed on a substrate, various attempts have been made thus far. For example, in Japanese Patent Laid-Open No.10(1998)-268522, a method of forming a conductive pattern is disclosed, in which patterning is performed by use of a positive photoresist on a substrate, and the substrate is subjected to electroless plating thus forming the conductive pattern on an exposed substrate.
In Japanese Patent Laid-Open No. 11(1999)-339672, a method of manufacturing an image display device is disclosed, in which photoresist is coated on a substrate and patterning is performed, and then an electrode is formed by use of an electroplating method, an electroless plating method, or both the electroplating method and the electroless plating method, followed by removing of the photoresist.
In Japanese Patent Laid-Open No. 11(1999)-231335, a method of manufacturing a substrate with a buried electrode is disclosed, in which a silicon dioxide film deposited on the substrate is patterned, and an electrode is formed on the exposed substrate by use of an electroless plating method.
However, any of the methods described above have not been satisfactory in terms of achieving a large screen, a high definition, an improved manufacturing yield and a reduced manufacturing cost while minimizing a propagation delay of a display device including a TFT structure.
The present invention was made in consideration of the foregoing problems.